Cadence Recruitment Drive 2026 | Cadence Hiring Electrical Engineer

www.djobbuzz.com 12 Mar 2026

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Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.
Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For.  Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.
Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

We are looking for strong technical team lead for IP Integration, subsystem creation, and QA for our SSG IP Integration and QA engineering team.
The role would include working with existing RTL, integration of PHYs and controllers to create sub-systems, and addition of new features.

EXP: 8-15 years Equivalent or Relavent
College education in Electronics Engineering or Computer Engineering
Candidate should be proficient in ASIC development flows like RTL design flow steps like RTL coding, Simulation, compilation/testbench validation, Synthesis, Timing, DFT, lint, CDC, LEC etc.
Familiarity with Power Flow (UPF/CPF).
Experience with functional simulation using Verilog/System Verilog and ability to debug existing Verilog/System Verilog test cases with little or no help from the designer
Good in Scripting languages(Shell, Perl, TCL, Python) and automation of design database qualification and packaging. Checks and validation of package consistency.
Bug reporting and resolution closure with IP providers
Ability to debug synthesis/timing analysis constraints, reports, logs
Ability to learn new tools/flows and develop methodology if needed.
8+ years of relevant experience in Digital Design and verification.

Ensuring various customer configurations are clean as part of verification regressions, and ensuring design is clean for all QA aspects in both Front End and Back End (these includes items like being Timing/LINT/RDC/CDC clean, consistency checks for all IP views etc.
A critical part of this role is for the technical lead to also oversee the adoption and roll out of Agentic AI initiatives into all aspects of IP Integration and QA including multi-agent connections in CDNS EDA flows.
They will work closely with various RnD IP leaders and Central Engineering teams around the world to ensure integration and release of IPs are handled on time and with Quality.
The lead should also be able to identify constant process improvement and automation to increase the efficiency of the entire RnD IP release process.
The role will include people management, and the lead would be responsible for technical and personal growth of their team.
This is a highly visible role as it is serves as a critical final touchpoint from RnD to Customers and our IP teams success hinges on the efficiency and throughput of this team.