Cadence Recruitment Drive 2025 | Cadence Hiring Mechanical Engineer

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Company Name
Cadence
Company Website
http://www.cadence.com/
Experience
1-4 Years
Job Role
Design Engineer
Job Type
  • Experienced
Job Location
  • Hyderabad
Skills
  • Good Communication Skill
Education
  • BE/BTech
Branch
  • Mechanical Engineering
Job will expire on
10 Aug 2025

About Company

Cadence is a pivotal leader in electronics and system design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For eight years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. 

Eligibility Criteria

  • BE/BTECH---1-4 yrs
  • Very good knowledge on SCAN/ATPG/JTAG/MBIST
  • Experience with one or more chip tape out that includes chip ATE bring up.
  • Experience on gate level simulation with no timing and timing (SDF) simulations (ATPG/MBIST/JTAG)
  • Experience in Test structures for DFT, IP integration, ATPG fault models, test point insertion, coverage improvement techniques.
  • Experience in scan insertion techniques at block level and chip top level.
  • Experience on Memory BIST generation, insertion, verification on RTL/Netlist level.
  • Good knowledge and understanding in Analog PHY and Analog Macro tests.

Job Description

  • Good knowledge and understanding on JTAG for IEEE 1149.1/IEEE1149.6 standards.
  • Good knowledge on test mode timing constraints
  • Good knowledge about running block level and chip STA flows.
  • Cross domain knowledge to resolve DFT issues with design, synthesis, physical design, STA team.
  • Proficiency in industry standard tools for scan insertion, ATPG, MBIST and JTAG (preferable Cadence/Tessent tools)
  • Experience with post-silicon bring up and debug on ATE.
  • Good knowledge on Perl/Tcl scription skills
  • Very good team player capabilities and excellent communication skills to work with a variety of teams across the global organization.
  • High sense of responsibility and ownership within the team for successful tape out and post-silicon bring up of project.

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